[International] Chip execs see 20 nm variants, 3-D ICs ahead


Next-generation 20 nm processes can support optimized versions for low power and high performance, according to an IBM expert. GlobalFoundries will decide in August whether or not it will offer such variations.


Those were just two data points from wide ranging discussions at the GSA Silicon Summit here. Separately, executives said a variety of 3-D ICs will hit the market in 2014 despite numerous challenges, and CMOS scaling is slowing down but still viable through a 7 nm node.


“Recently TSMC said at 20 nm there are no significant differences [in process optimizations], but I don’t believe that,” said Subramanian Iyer, an IBM fellow and chief technologist in its microelectronics division. “I believe at same node you can have two [different variations],” he said in a keynote here.


Indeed, GlobalFoundries is debating whether it wants to offer high performance and low power variants of a 20 nm process it is putting in place today.


“We are still talking with lead customers to see what is the right thing to do, and there’s a lot of interest in performance and power trade-offs,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries in a brief interview with EE Times.


The variations available at 20 nm may be relatively narrow and may not be economically viable, he said. Iyer of IBM said TSMC’s decision to offer one flavor of 20 nm may have been more of an economic than a technical decision.


The follow-on 14 nm process using FinFETs will open up greater opportunities for a high performance version at up to 0.9 volts and a low power variant at down to 0.6 volts, Kengeri said. In addition, the 14 nm node could offer as much as twice the typical benefits of moving to a new node.


The historic challenge of offering variations of a process is that each one requires a different set of unique and complex features added to the base process, said Iyer of IBM. “All the little features we have are like drugs, we can’t drop them without severe withdrawal symptoms,” he said.


3-D ICs coming in 2014

 Separately, executives said several types of 3-D ICs using through-silicon vias (TSVs) will be in production in 2014.


 “This is a game changer,” said Mark Brillhart, a packaging expert and vice president of technology and quality at Cisco Systems, moderating a panel here. “I think 3-D ICs will be a differentiator and they will proliferate into a lot of applications,” he said.


 “I never thought packaging would be exciting again, but it’s like 1996 with flip chip all over again,” Brillhart said.


 Qualcomm is “very happy with” dense 2.5-D Xilinx FPGAs “we are playing with in the lab” for product prototyping, said Nick Yu, vice president of engineering at Qualcomm. He predicted mobile applications processors for high-end smartphones will hit the market this year or next using TSVs to link to Wide I/O memories.


 “This 3-D technology is really powerful and we will see it in many places,” said Iyer of IBM which has already made working prototypes of server processors in TSV stacks with DRAMs.


 CPUs have 8-12 cores now “and want to go to 24 cores” with 3-D IC modules that stack DRAMs and heat sinks. IBM is also interested in “systems on an interposer,” 2.5-D modules that surround a processor with memory chips on a silicon substrate with de-coupling capacitors to improve power regulation, he said.


 “There’s a lot of good stuff happening in this area that will make a significant difference, and the same concepts are applicable in the mobile space with similar advantages,” he added.


The 3-D ICs also pose plenty of unsolved problems. They generate heat that engineers still don’t know how to dissipate, they require new test strategies and manufacturing tools and they require designers form new kinds of supply chains that collaborate on deeply detailed technical and business levels.


 “Cost is biggest issue of 3-D ICs right now,” said Yu of Qualcomm.


 He said he is not convinced TSMC’s proposed end-to-end 3-D service will be the lowest cost offering it promises. Different supply chains will be required for different 3-D products, he added.


 “Equipment costs are a big factor in our unit costs,” said Rich Rice, senior vice president of engineering and sales at ASE Group which is installing bonding/de-bonding, wafer thinning and other systems to handle the so-called middle steps of the 3-D process. “Even on the more traditional back-end we have a stiff cap ex burden when we start to ramp this capability up,” Rice said.


 A spokesman for Applied Materials noted the need for new 3-D systems comes while capital equipment makers are also trying to prepare systems for 450 mm wafers and the 20 and 14 nm nodes.


 Cisco’s Brillhart said he is concerned the many sometimes competing companies that need to come together to enable 3-D ICs find profitable ways to collaborate. “I’ve worked on too many programs where one of the partners in the supply chain became unprofitable and the technology went away,” he said.


Moore’s Law more slowly

 The good news is experts see no fundamental barriers to scaling process technology down to at least 7 nm. The bad news is “as you go to smaller nodes the benefits of scaling are being eroded significantly,” said Iyer of IBM.


 The culprit is the lack of any new lithography techniques. Today’s 193 nm immersion lithography systems are being asked to create 22 and even 14 nm features.


 “This does not come free, the costs are becoming formidable,” Iyer said. “Complex patterning solutions are the cause of the angst we are having,” he added.


Indeed costs of lithography will jump significantly at 20 nm and soar at 14 nm, said Kengeri of GlobalFoundries. The additional complexities and process and design costs are among the reasons the traditional two-year cadence between nodes is lengthening, he said.


 It took three extra quarters for the industry to qualify the 32/28 nm node and the ramp for the technology was a quarter longer than usual, Kengeri said. “Things are slowing down,” he added.


 According to a Merrill Lynch report, the cost of a single SoC project could bloat to $250 million at the 14 nm node, said Roawen Chen, vice president of manufacturing at Marvell Semiconductor. Masks costs alone will be about $7 million and the time from tapeout to first silicon could expand to six months, he said.


 “The bottom line is its becoming very expensive,” Chen said.


 The good news is one IBM researcher showed ways to make devices with as few as 25 atoms, opening the door to a 7 nm, process node. “Until we get to 7 nm or so there are no fundamental issues we see,” said Iyer.


Source: EETimes