[International] Intel describes 22-nm SoC process, not chips

 

Intel provided the first look at the system-on-chip variant of its 22-nm process technology in a talk at the Intel Developer Forum here Thursday (Sept. 13). However, it declined to provide details on the Atom-based SoCs for tablets and smartphones that will be made in that process.

 

“It’s fair to say Intel didn’t have much of a focus four or five years ago on SoCs, but that’s changed,” said Mark Bohr, director of Intel’s technology and manufacturing group in a process technology talk. “The success of Medfield [Intel’s 32-nm smartphone platform] shows we are learning to do it right, and I think we will have a technology advantage at 22 nm,” he said.

 

Intel showed at IDF six smartphones and four Windows 8 tablets using the Medfield SoC, made in an SoC variant of its 32-nm process. “There’s a lot more in the pipeline,” said Ticky Thakkar, a lead Atom designer in a separate talk on the mobile chips.

 

The company is already shipping to OEMs a 2-GHz version of Clover Trail, a follow on 32nm dual-core processor with boosted graphics. A 1.8-GHz version for tablets is also in the works.

 

Next up is Bay Trail, Intel’s first 22-nm SoC for tablets and smartphones, expected to debut at IDF Beijing. “You’ll have to wait until next year to hear about it,” said Thakkar.

 

In a separate talk, Bohr described P1271, the 22-nm SoC process to be used for Bay Trail. It differs from the 22-nm CPU process now used for Intel’s Ivy Bridge processors by offering lower leakage logic transistors, higher voltage I/O transistors, denser upper layer interconnects and a set of precision resistors, capacitors and inductors.

 

Intel showed it 22-nm SoC process menu.

 

“It’s not one set of features, but a menu of feature options—transistors, I/O, interconnects, passive elements and embedded memory,” Bohr said. “The [SoC] transistors go down to much lower leakage levels, but give up some performance,” he said.

 

The process has significantly better analog characteristics than Intel’s current 32-nm planar process. Designs make heavy use of 80-nm pitch features in lower metal layers, because they are the smallest features Intel can make at 22 nm without needing double patterning, he added.

 

Intel is running the process at three fabs, two in the U.S. and one in Israel. It will ramp soon in two other fabs.

 

Intel showed performance and power characteristics of its 22-nm SOC transistors.

 

Source: EETimes

 

 

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