[International] Moore's Law threatened by lithography woes

 

Moore's Law, the engine of semiconductor innovation for decades, is losing steam due to delayed introduction of next-generation extreme ultraviolet lithography. That was the verdict of experts at the 2012 International Symposium on Extreme Ultraviolet Lithography.

EUV systems need light sources that are nearly 20 times more powerful than the ones used today to lay down patterns on next-generation chips that target sizes as small as 14 nm, Following a global symposium on the topic here, a group of lithography experts said that they hope to have the 200W EUV light sources by 2014—but it may take more time.

Using less powerful light sources, researchers at the Interuniversity Microelectronics Centre (IMEC) here have created about 3,000 wafers using EUV in the past year. But the throughput of the multimillion dollar systems are still 15-30 times too slow for commercial chip makers such as Intel, Samsung and Taiwan Semiconductor Manufacturing Co.

Researchers have improved the power of light sources 20-fold over the past three years. But they must make similar heroic improvements in the next two years before EUV is ready for production, said Kurt Ronse, IMEC's director advanced lithography program, reporting on the conclusions of an EUV symposium in Brussels. The group also called for development of 500-1,000W EUV light sources by 2016.

As a result of the EUV delays “the [semiconductor] industry is no longer taking full steps, but implementing half nodes,” Ronse said. “They still call it 14 nm but it’s probably more like 16 or 17 nm,” he said.

Scaling slowed

For example, SRAM cells won’t get a full 50 percent shrink at 14 nm without EUV, Ronse said. That’s because multiple patterning has some limits in how closely it can place features.

“They can only catch up if EUV becomes available,” Ronse said. “There [are] lot[s] of resources going into development of light sources, so there is definitely a way to get there, but it’s hard to estimate if it will be in two years,” he said.

Intel and TSMC recently committed billions of dollars to ASML (Eindhoven, Netherlands) which is developing the EUV systems.

Intel also recently said it expects to make 14-nm chips next year and could make 10-nm processors in 2015 using existing immersion lithography. Without EUV, Intel believes it will have to write as many as five immersion patterns on a chip which will take more time and money but is still economical.

IMEC now gets more than 60 percent of production time with its ASML NXE 3100 EUV system installed here. “We had quite some bumpy behavior in the first six months with average up time declining from 50 to 10 percent,” due to problems with an older light source, he said.

In its trials, IMEC has achieved device resolution down to 16-nm half pitch with EUV. “EUV is most likely not going to be used for all layers [in a chip], but for some critical layers and will have to be aligned well for immersion,” said Ronse.

Alignment is also a problem. To date, IMEC has achieved alignment within 6 nm of EUV and immersion layers on a chip. It needs to get down to alignment within 2 to 3 nm, he said.

Source: EETimes

 

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