VIEWPOINT - Maximizing the value of your IP (Kathryn Kranen)

 

Some amazing statistics: Third-party semiconductor IP is now a $1 billion per year business, with thousands of suppliers. One-third of all logic in a design is now reused legacy IP, and that figure will grow to 50 percent by 2015.

 

The reasoning behind this is simple: More integration of IP into new designs increases productivity accordingly, or does it?

 

We hear a lot about "leveraging" IP to address new applications, speed production, and tailor products to meet customers' needs. In a perfect world this makes sense, but when IP originally created for other purposes is integrated into a new design there are numerous factors to consider.

 

Most importantly, adding existing IP means modifying your RTL, a high-cost/high-risk proposition. Ron Collett, President and CEO of Numetrics which provides software and services to manage IC development risks, recently wrote that "making 30 percent of your design from reused IP blocks doesn't mean you're going to be 30 percent more productive at the end of the project. That's because IC design teams tend to underestimate the work needed to implement the reused IP," a dilemma illustrated in the following chart:

In fact, Collett wrote, even a small percentage of reuse can add outsized effort to a development project. "For example, if you add one new block of 600,000 gates to a 6 million-gate design, you're adding 10 percent to the IC but increasing the effort required on the project by 24 percent. Adding 10 percent new circuitry to all blocks in that 6 million-gate design —with 90 percent of each block being reused— doubles the effort required on the project, even though it increases the IC size by just 10 percent to 6.6 million gates."

 

Now from our point of view as verification experts, we are witnessing these challenges every day, as our customers strive to reach definitive answers to crucial questions relating to IP reuse and design verification. For example, there typically exists an enormous verification environment that is larger than the RTL itself and just as difficult to modify as the code; and documentation can be incomplete, ambiguous or even inaccurate, and may not even correlate to the original designer's intentions.

 

Given these obstacles, how does one go about answering very basic questions related to reuse, such as: What will break if we change this section of the RTL? Can this block be configured for the new application? What is the minimum latency of this path? Can this event ever happen? Etc.

 

The worst part is that these same questions come up over and over again, leading to time-consuming and costly delays while the verification team wrestles with debugging a verification environment that is separate from the RTL, attempts to recreate dynamic simulation events, and reproduces scenarios the original designer at one point had in his or her head.

 

A revolutionary approach to answering these time-wasting reuse questions is to decouple the RTL from the large, unwieldy, constrained-random simulation testbench and extract answers from the design itself, through a new application of formal verification technology called Behavioral Indexing.

 

While specifications can tell you what you intended the design to do, and simulation provides empirical results to stimulus, it's the RTL itself that is the authority of what it can and cannot do. Formal can extract this information. Some of our customers who are suppliers of third-party IP encounter questions from their customers, trying to deduce whether a certain set of events can happen. And, as you might expect, the IP designer cannot determine the input sequence needed to produce an answer with simulation. Fortunately, Jasper's formal solutions help them pinpoint the scenario of interest and swiftly resolve the customer's issue.

 

There is no doubt that leveraging IP for reuse is here to stay — the economic and time-to-market advantages are too enormous to forego. However, there are serious challenges to overcome given the high cost of verification and the risk of collateral design damage consequential to RTL modification. Through innovative use of formal we now have the ability to both improve the original design, and more easily extract answers to specific reuse questions. Combined with advances in internal IP reuse methodologies and practices, these new technologies can significantly maximize the value of a company's IP investment.

 

About the author:


Kathryn Kranen is president and CEO of Jasper Design Automation Inc. (Mountain View, Calif.).

She is responsible for leading Jasper's team in successfully bringing the company's pioneering technology to the mainstream design verification market.

 

She has 20 years EDA industry experience and a proven management track record. While serving as president and CEO of Verisity Design, Inc., US headquarters of Verisity Ltd., Kathryn and the team she built created an entirely new market in design verification. (Verisity later became a public company, and was the top-performing IPO of 2001.)

 

Prior to Verisity, Kathryn was vice president of North American sales at Quickturn Systems. She started her career as a design engineer at Rockwell International, and later joined Daisy Systems, an early EDA company.

 

Kathryn graduated Summa cum Laude from Texas A&M University with a B.S. in Electrical Engineering. Kathryn is serving her fifth term on the EDA Consortium board of directors, and was elected its vice chairperson. In 2005, Kathryn was recipient of the prestigious Marie R. Pistilli Women in Electronic Design Automation (EDA) Achievement Award.

 

Source: EETimes

 

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