[International] Jedec readies DDR4 memory spec


SAN FRANCISCO—The Double Data Rate 4 (DDR4) memory chip standard will include three data width offerings, differential signaling, data masking and a new termination scheme, according to the Jedec Solid State Technology Association, the standards developer that creates the DDR standards.


The DDR4 standard is expected to be published in mid-2012 and will offer significant advancements in performance with reduced power usage as compared to previous generation technologies, Jedec (Arlington, Va.) said Monday (Aug. 22). When published, the DDR4 standard will be available on Jedec's website, the organization said.  www.jedec.org.


DDR4 is being developed with a range of features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products, Jedec said. Its speed, voltage and architecture are all being defined with the goal of simplifying migration and facilitating adoption of the standard, according to the organization.


Jedec said a DDR4 voltage roadmap has been proposed that will facilitate customer migration by holding VDDQ constant at 1.2V and allowing for a future reduction in the VDD supply voltage. DDR4 will help protect against technology obsolescence by keeping the I/O voltage stable, Jedec said.


The per-pin data rates, over time, will be 1.6 giga transfers per second to an initial maximum objective of 3.2 giga transfers per second, Jedec said. With DDR3 exceeding its expected peak of 1.6 GT/s, it is likely that higher performance levels will be proposed for DDR4 in the future, Jedec said.


Other performance features planned for inclusion in the DDR4 standard are a pseudo open drain interface on the DQ bus, a geardown mode for 2667 Mhz data rates and beyond, bank group architecture, internally generated VrefDQ and improved training modes, Jedec said.


Other highlights of the DDR4 standard will include:


• New JEDEC POD12 interface standard for DDR4 (1.2V).

• Three data width offerings: x4, x8 and x16.

• Differential signaling for the clock and strobes.

• New termination scheme versus prior DDR versions: In DDR4, the DQ bus shifts termination to VDDQ, which should remain stable even if the VDD voltage is reduced over time.

• Nominal and dynamic ODT: Improvements to the ODT protocol and a new Park Mode allow for a nominal termination and dynamic write termination without having to drive the ODT pin .

• Burst length of 8 and burst chop of 4.

• Data masking.

• DBI: to help reduce power consumption and improve data signal integrity, this feature informs the DRAM as to whether the true or inverted data should be stored.

• New CRC for data bus: Enabling error detection capability for data transfers – especially beneficial during write operations and in non-ECC memory applications.

• New CA parity for command/address bus: Providing a low-cost method of verifying the integrity of command and address transfers over a link, for all operations.

• DLL off mode supported.

•   Three data width offerings: x4, x8 and x16

•   New JEDEC POD12 interface standard operations.
•   DLL off mode supported


Jedec said it plans to host a DDR4 technical workshop following the publication of the standard. More information and details will be announced coincident with publication.
“Numerous memory device, system, component and module producers are collaborating to finalize the DDR4 standard, which will enable next generation systems to achieve greater performance with lower power consumption," said Joe Macri, chairman of Jedec's JC-42.3 subcommittee for DRAM memories, in a statement.


Source: EETimes