[International] GlobalFoundries fabs 20-nm test chip


SAN JOSE, Calif. – GlobalFoundries taped out a 20nm test chip using design tools from Cadence Design Systems, Magma Design Automation, Mentor Graphics and Synopsys. The test used double patterning and was implemented with each EDA partner contributing a large placed and routed design.


The test chip supported double patterning library preparation, placement, clock tree synthesis, hold fixing, routing and post-route optimization. The design flow supported extraction, static timing analysis and physical verification.


GlobalFoundries said it will make the test chip and its libraries including complete flow scripts available to customers who wish to evaluate 20nm technology.


Source: EETimes